The present invention relates to a nonvolatile memory using resistance change accompanied with phase change and a method for fabricating the same.
As a known semiconductor memory device using a chalcogenide material, for example, semiconductor memory device is disclosed in U.S. Pat. No. 6,236,059. FIG. 5 is a cross-sectional view of the known semiconductor memory device using a chalcogenide material disclosed in U.S. Pat. No. 6,236,059.
Respective steps for fabricating a nonvolatile memory of FIG. 5 will be described. First, an interlayer insulating film 104 deposited over a silicon substrate 102 is patterned to form a contact hole 106 reaching the silicon substrate 102. Then, polysilicon (not shown) is deposited over the interlayer insulating film 104 by thermal CVD to fill the contact hole 106 and then part of polysilicon located on the interlevel insulating film 104 is removed by CMP. Thereafter, a recess is formed by selectively etching the polysilicon to remove upper part of the polysilicon in the contact hole 106. Thus, a plug 108 is formed.
Then, a TiN film (not shown) is deposited over the interlevel insulating film 104 to fill the recess and part of the TiN film located on the interlevel insulating film 104 is selectively removed by CMP. Furthermore, etching is performed to remove upper part of the TiN film filling upper part of the contact hole 106, thereby forming a recess. Thus, a resistance heating element film 110 made of TiN is formed on the plug 108. An SiN film (not shown) is deposited over the interlevel insulating film 104 by CVD to fill the recess and then part of the SiN film located on the interlevel insulating film 104 is removed by selectively polishing the part by CMP. Thus, an interlevel insulating film 112 filling the recess is formed. Thereafter, in a center part of the interlevel insulating film 112, a small hole reaching the resistance heating element film 110 is formed. Then, chalcogenide (GeSbTe, which is not shown) used as a memory material is deposited by sputtering to fill the hole. Thereafter, part of GeSbTe located on the interlevel insulating film 104 is selectively removed by CMP to form a storage element film 114. Then, a barrier metal 116 and an interconnect 118 covering the storage element film 114 and parts of the interlevel insulating film 112 located around the storage element film 114 are formed.
Of the above-described steps, the steps of forming the contact hole 106, the plug 108, the barrier metal 116 and the interconnect 118 can be performed according to a logic process. That is, in a technique disclosed in U.S. Pat. No. 6,236,059, the storage element film 114 is buried in the interlevel insulating film 112, thereby improving consistency with a logic process. However, the thickness of the interlevel insulating film 104 in a logic section is increased according to the thickness of a storage element buried therein. Accordingly, the depth of a contact in the logic section is increased, so that an interconnect delay is increased.
As has been described, in a known method, although it is possible to make some of the steps for fabricating a storage element have consistency with a logic process, a complicated step has to be performed separately from the logic process.
Specifically, the step of filling the recess in the plug 108 with the TiN film, i.e., a low resistance material and flattening the film, the step of etching the TiN film to form a recess, the step of filling the SiN film and flattening the film, the step of performing lithography and etching to the filled SiN film to form a hole, and the step of filling the hole with a memory material and flattening the material have to be performed separately from a logic process. As has been described, process steps for integrating storage elements are complicated and make reduction in the size of each element difficult.